3d7608 & 3d7612 8-bit & 12-bit programmable pulse generators ( series 3d7608 & 3d7612: parallel interface ) features packages / pinouts ? all-silicon, low-power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? programmable via latched parallel interface ? increment range: 0.25ns through 800us ? pulse w i dth tolerance: 1% (see table 1) ? supply current: 8ma typical ? temperature stability : 1.5% max (-40c to 85c) ? vdd stability : 0.5% max (4.75v to 5.25v) functional description the 3d7608 & 3d7612 devices ar e versatile 8- & 12-bit programmable monolithic pulse generators. a rising-edge on the trigger input (trig) initiates the pulse, which is presented on the output pins (out,outb). the pulse width, programmed via the parallel interface, can be varied over 255 (3d7608) or 4095 (3d7612) equal steps according to the formula: t pw = t inh + addr * t inc where addr is the programmed address, t inc is the pulse width increment (equal to the device dash number), and t inh is the inherent (address zero) pulse width. the device also offers a reset input (res), which can be used to terminate the pulse before the programmed time has expired. the all-cmos 3d7608 & 3d7612 integrated circuits hav e been designed as reliable, economic alternatives to hybrid ttl pulse generators. the 3d7608 is o ffered in a standard 16-pin soic, and the 3d7612 is offered in a standard 20-pin sol. table 1: part number specifications d a ta delay devices, i n c. ? 3 pin descriptions trig trigger input res reset input out pulse output outb complementary pulse output ae address enable input p0-p11 address inputs vdd +5 volts gnd ground nc do not connect externally f o r mechanical dimensions, click here . f o r package marking details, click here . 1 2 3 4 5 7 8 16 15 14 13 12 10 9 tr i g res p0 p2 p4 nc gnd vdd out out b p1 p3 p7 a e 3d 7608r -x x so ic 6 11 p6 p5 7 14 p8 p7 1 2 3 4 5 6 8 9 10 20 19 18 17 16 15 13 12 11 tr i g re s p0 p2 p4 p6 nc p1 0 g nd vdd ou t ou t b p1 p3 p5 p9 a e p11 3d7612w -x x s o l note: a n y increment betw een 0.25ns and 800us (50us for the 12-bit generator) not show n is also av ailable as a standard dev i ce. pa rt # (8-bit) pa rt # (12-bit) pul se wi dth increment m aximum p.w. (8-bit) m aximum p.w. (12-bit) p a r t # (8-bit) pul se wi dth increment m aximum p.w. (8-bit) 3 d 7 6 0 8 r - 0 . 2 5 3 d 7 6 1 2 w - 0 . 2 5 0.25ns 0.12ns 73.25ns 3ns 1.03us 10ns 3d7608r-100k 100us 50us 25.5ms 260us 3 d 7 6 0 8 r - 0 . 5 3 d 7 6 1 2 w - 0 . 5 0.50ns 0.25ns 137.5ns 3ns 2.05us 21ns 3d7608r-200k 200us 100us 51.0ms 510us 3 d 7 6 0 8 r - 1 3 d 7 6 1 2 w - 1 1.0ns 0.5ns 265ns 3ns 4.10us 41ns 3d7608r-500k 500us 250us 128ms 1.3ms 3 d 7 6 0 8 r - 2 3 d 7 6 1 2 w - 2 2.0ns 1.0ns 520ns 6ns 8.19us 82ns 3d7608r-800k 800us 400us 204ms 2.1ms 3 d 7 6 0 8 r - 5 3 d 7 6 1 2 w - 5 5.0ns 2.5ns 1.28us 13ns 20.5us 205ns 3 d 7 6 0 8 r - 1 0 3 d 7 6 1 2 w - 1 0 10ns 5.0ns 2.56us 26ns 41.0us 410ns 3 d 7 6 0 8 r - 2 0 3 d 7 6 1 2 w - 2 0 20ns 10ns 5.11us 52ns 81.9us 819ns 3 d 7 6 0 8 r - 5 0 3 d 7 6 1 2 w - 5 0 50ns 25ns 12.8us 128ns 205us 2.1us 3 d 7 6 0 8 r - 1 0 0 3 d 7 6 1 2 w - 1 0 0 100ns 50ns 25.5us 255ns 410us 4.1us 3 d 7 6 0 8 r - 2 0 0 3 d 7 6 1 2 w - 2 0 0 200ns 100ns 51.0us 510ns 819us 8.2us 3 d 7 6 0 8 r - 5 0 0 3 d 7 6 1 2 w - 5 0 0 500ns 250ns 128us 1.3us 2.05ms 21us 3 d 7 6 0 8 r - 1 k 3 d 7 6 1 2 w - 1 k 1.0us 0.5us 255us 2.6us 4.10ms 41us 3 d 7 6 0 8 r - 2 k 3 d 7 6 1 2 w - 2 k 2.0us 1.0us 510us 5.2us 8.19ms 82us 3 d 7 6 0 8 r - 5 k 3 d 7 6 1 2 w - 5 k 5.0us 2.5us 1.28ms 13us 20.5ms 205us 3 d 7 6 0 8 r - 1 0 k 3 d 7 6 1 2 w - 1 0 k 10us 5.0us 2.55ms 26us 41.0ms 410us 3 d 7 6 0 8 r - 2 0 k 3 d 7 6 1 2 w - 2 0 k 20us 10us 5.10ms 52us 81.9ms 819us 3 d 7 6 0 8 r - 5 0 k 3 d 7 6 1 2 w - 5 0 k 50us 25us 12.8ms 128us 205ms 2.1 ms ? 2006 data delay dev i ces doc #06009 data delay devices, inc. 1 5/8/2006 3 mt. prospect ave. clifton, nj 07013
3d7608 & 3d7612 application notes general information figure 1 illustrates the main functional blocks of the 3d7608 & 3d7612. since these devices are cmos designs, all unused input pins must be returned to well-defined logic levels, vdd or ground. the pulse generator architecture is comprised of a number of delay cells (for fine control) and an oscillator & counter (for coarse control). each device is individually trimmed for maximum accuracy and linearity throughout the address range. the change in pulse width from one address setting to the next is called the increm ent , or lsb. it is nominally equal to the device dash number. the minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width . for best performance, it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. also, signal traces should be kept as short as possible. pulse width accuracy there are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. the first is the differential nonlinearity (dnl), also referred to as the increment error. it is defined as the deviation of the increment at a given address from its nominal value. for most dash numbers, the dnl is within 0.5 lsb at every address (see table 1: pulse width step). the integrated nonlinearity (inl) is determined by first constructing t he least-squares best fit straight line through the pulse-width-versus- address data. the inl is then the deviation of a given width from this line. for all dash numbers, the inl is within 1.0 lsb at every address. the relative error is defined as follows: e rel = (t pw ? t inh ) ? addr * t inc where addr is the address, t pw is the measured width at this address, t inh is the measured inherent width, and t inc is the nominal increment. it is very s i milar to the inl, but s i mpler to calculate. for most dash numbers, the relative error is less than 1.0 lsb at every address (see table 1). the absolute error is defined as follows: e abs = t pw ? (t inh + addr * t inc ) where t inh is the nominal inherent delay. the absolute error is limited to 1.5 lsb or 3.0 ns, whichever is greater, at every address. the inherent pulse width error is the deviation of the inherent width from its nominal value. it is limited to 2.0 ns from the nominal inherent pulse width of 10 ns. pulse width stability the characteristics of cm os integrated circuits are strongly dependent on power supply and temperature. the 3d7608 & 3d7612 utilize novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature. with regard to stability, the output pulse width of the 3d7608 & 3d7612 at a given address, addr, can be split into two components: the inherent pulse width (t inh ) and the relative pulse width (t pw - t inh ). these components exhibit very different stability coefficients, both of which must be considered in very critical applications. the thermal coefficient of the relative pulse width is limited to 250 ppm/c, which is equivalent to a variation, over the -40c to 85c operating range, of 1.5% from the room-tem perature pulse width. this holds for all dash numbers. the thermal coefficient of the inherent pulse width is nominally +10ps/c for dash numbers less than 1, and +15ps/c for all other dash numbers. the power supply sensitivity of the relative pulse width is 0.5% over the 4.75v to 5.25v operating range, with respect to the pulse width at the nominal 5.0v power supply. this holds for all dash numbers. the sensitivity of the inherent pulse width is nominally ?1ps/mv for all dash numbers. it should also be noted that the dnl is also adversely affected by thermal and supply variations, particularly at the msl/lsb crossovers (ie, 63 to 64, 127 to 128, etc). doc #06009 data delay devices, inc. 2 5/8/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7608 & 3d7612 doc #06009 data delay devices, inc. 3 5/8/2006 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) trigger & reset timing figure 2 shows the timing diagram of the device when the reset input (res) is not used. in this case, the pulse is triggered by the rising edge of the trig signal and ends at a time determined by the address loaded into the device. while the pulse is active, any additional triggers occurring are ignored. once the pulse has ended, and after a short recovery time, the next trigger is recognized. figure 3 shows the timing for the case where a reset is issued before the pulse has ended. again, there is a short recovery time required before the next trigger can occur. address update the 3d7608/3d7612 can operate in one of two addressing modes. in the transparent mode (ae held high), the parallel address inputs must persist for the duration of the output pulse, in accordance with figure 4. in the latched mode, the address data is stored internally, which allows the parallel inputs to be connected to a multi-purpose data bus. timing for this mode is also shown in figure 4. 8- or 1 2 -b it l a t ch a e tr g ad dr en a b le trigger pu l s e o u t figure 1 : f unctional block dia g ra m ou t ou tb re s re s e t de la y li ne os ci lla t or/ cou n t e r inpu t log i c outp ut log i c p0 p7 p1 1 p1 0 p9 p8 p1 b i t - shi f t l ogic tri g figure 2 : t i ming dia gr am (res = 0 ) t tw t rto t id t pw ou t outb tr i g figur e 3 : t i m ing di a g ra m ( w it h re s e t ) t tw t rt r t id t rd out outb re s t rw
3d7608 & 3d7612 application notes (cont?d) f i g u r e 4: a d d r ess up d a t e t aw val i d t ds t dh t oa t at1 tr i g out ad d r ae t at2 val i d t oa t at1 tr i g out ad d r val i d lat c hed m ode trans parent m ode (a e = 1) doc #06009 data delay devices, inc. 4 5/8/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7608 & 3d7612 device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 0 1 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (-40c to 85c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s static supply current* i dd 8 . 0 1 2 . 0 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih 1 . 0 a v ih = v dd low level input current i il 1 . 0 a v il = 0v high level output current i oh - 3 5 . 0 - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 1 5 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 . 0 2 . 5 n s c ld = 5 pf *i dd (dy namic) = 2 * c ld * v dd * f input capacitance = 5 pf ty pical w here: c ld = average capacitance load/output (pf) output load capacitance (c ld ) = 25 pf max f = trigger frequency (ghz) table 4: ac electrical characteristics (-40c to 85c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s r e f e r t o trigger width t tw 5 ns figure 2 & 3 trigger inherent delay t id 5 ns figure 2 & 3 output pulse width t pw n s f i g u r e 2 re-trigger time t rt o 3 n s f i g u r e 2 reset width t rw t b d n s f i g u r e 3 res e t to output low t rd 5 n s f i g u r e 3 end of reset to next trigger t rt r 3 n s f i g u r e 3 ae width t aw 1 2 n s f i g u r e 4 data setup to ae low t ds 1 0 n s f i g u r e 4 data hold from ae low t dh 3 n s f i g u r e 4 output low to ae high t oa 3 n s f i g u r e 4 data valid to trigger t at 1 1 0 n s f i g u r e 4 ae high to trigger t at 2 1 0 n s f i g u r e 4 doc #06009 data delay devices, inc. 5 5/8/2006 3 mt. prospect ave. clifton, nj 07013
3d7608 & 3d7612 typical applications fig u re 5 : pr og r a mma ble os cilla t o r 3 d 76 08 or 3 d 76 12 trig res ou t ou t b a dd r a e en a e a dd r fo u t en fout fout = 1 / ( t pw + t id + t no r ) t id + t no r figu r e 6: p r ogra mmable de la y l i n e 3d 76 08 / 1 2 r- e d ge de l a y trig re s ou t ou t b a dd r a e d- f f se t b d q qb re sb ck d- f f se t b d q qb re sb ck +5 +5 0v 0v in a ef a dd r out trig re s ou t ou t b a dd r a e 3d 76 08 / 1 2 f-edg e de l a y in out t pw r + t id + t ff t pw f + t id + t ff a er doc #06009 data delay devices, inc. 6 5/8/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7608 & 3d7612 doc #06009 data delay devices, inc. 7 5/8/2006 3 mt. prospect ave. clifton, nj 07013 silicon device automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 20ns period: per in = 2 x prog?d pulse width note: the above conditions are for test only and do not in any way restrict the operation of the device. ou t tri g in ref tri g f i g u re 7: t e st set u p de v i ce un de r test ( d ut) dig i tal s c ope/ ti m e i nte r v a l cou nter pu lse ge n e rator ou t tr i g com p u t e r sys tem pr in te r figur e 8 : t i ming dia g r a m t id t pw per in pw in t rise t fall 0. 6 0. 6 1. 5 1. 5 2. 4 2 . 4 1. 5 1. 5 v ih v il v oh v ol inp u t si g n al out p ut si g n al
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